Huawei has unveiled a new semiconductor concept, the Tau (τ) Scaling Law, marking a bold effort to redefine how chip performance is measured in the AI era.
Rather than focusing on traditional transistor miniaturization, Huawei's approach prioritizes reducing data transmission latency inside chips through a system-level design strategy known as LogicFolding.
For decades, the semiconductor industry has followed Moore's Law, steadily improving performance by shrinking transistors and packing more of them onto a chip.
This approach has been driven by companies like TSMC and supported by advanced design firms such as NVIDIA, which rely on ever-smaller manufacturing nodes.
However, as physical and economic limits of scaling become more difficult to overcome, Huawei argues that the industry is entering a new phase. Its Tau Scaling framework shifts the focus from "how small transistors can get" to "how fast information moves across a chip."
The key idea is a shift from flat 2D chip layouts to 3D stacked architectures, reducing signal-travel distances and improving efficiency. Huawei claims this approach could eventually deliver transistor densities equivalent to 1.4nm-class nodes by 2031, despite restrictions on advanced chipmaking tools.
While analysts remain cautious about its real-world impact, they acknowledge that Tau Scaling reflects a broader industry shift toward system-level innovation as Moore's Law slows down.
Reporter: Xie Hongzhou
Cameraman: Xie Hongzhou
Video & Poster: Deng Yingheng
